The telephone switching matrix can be of two forms, a time matrix or a space matrix. A space matrix is essentially a hardwired connection whereas a time matrix involves some minimal time delay in order to provide the switching. One form of a time matrix is a time slot interchange (TSI) which collects data in a given transmission frame, stores the data and then outputs the data in a subsequent frame. During the subsequent frame, the data is output in a different sequence than when it was received. A description of a TSI switch can be found in U.S. Pat. No. 4,112,258, issued to H. G. Alles.
In most telephone transmission protocols, the information is divided into a plurality of time domain multiplexed channels such that a predetermined number of channels exist in a given sample frame. Each channel consists of one sample of a linear value that is digitized and transmitted in a given time slot in the time frame. The preferential way of transmitting digital information is by pulse-code modulation (PCM).
A demultiplexer is typically disposed at the receiving end in the transmission system for receiving the digitized data stream and routing this information to a particular location which is a function of the time position in a particular frame. For example, if a frame were comprised of twenty-four channels, the PCM information in the first channel would be routed to a first location and the information in the second channel would be routed to a second location, the remaining channels being routed to a different location also. This continues for each frame with a first location receiving the information stored in the first channel of each frame, each channel distinguished by its time slot or position in the frame. It is necessary that the first time slot in each frame receive information for only one channel in each successive frame. This is normally a straightforward task when a system is synchronized with respect to frames. However, if information is to be switched in anything other than a T1 format, there is a potential that the integrity of the channels can be altered.
In a conventional TSI system, information is received and sequentially stored in a random access memory (RAM) in a given frame. In the next successive frame, this information is randomly output to a different channel in a different time slot. For example, if information in channel 1 of a collection frame is received from position A and this information is to be transmitted to a position B which corresponds to the second channel in the transmission frame, it would be necessary to access the stored information in the RAM in a different sequence than it was stored such that information received in the first channel during collection is transmitted in the second channel during transmission. This therefore requires a sequential writing of data to the RAM and random reading of the data in accordance with a predetermined connection pattern. Of course, the information is delayed by a single frame.
One of the disadvantages to a TSI system is that present day RAMs have a finite access time and capacity for writing of data to or reading of data from the RAM. Since the length of time for a given frame is defined by the T1 protocol, this provides a limitation for the amount of data that can be written to the RAM in a given frame and read from the RAM in a given frame. If the data to be switched exceeds this, it is then necessary to cascade a number of time matrices. This would be accomplished by interconnecting two time matrices with a space matrix which would result in a time-space-time matrix. This of course requires an additional frame of delay to go through the cascaded time matrix. This is a disadvantage from the time delay standpoint and also from the difficulties involved in interfacing the various matrices. These difficulties arise from the software involved in handling the switching configuration and also in the actual interconnection hardware.
The present invention overcomes the disadvantages of expanding a time matrix beyond the capabilities of the state-of-the-art access time for volatile memories to allow expansion of the system regardless of the access time of the memories.